Conventionally, there has been a demand for a sparse matrix having most of matrix elements which are 0 to suppress the used amount and the band width of a memory by retaining only non-zero components in the memory. Today, the demand is realized by managing only the values of the non-zero components and the position information thereof to suppress the used amount and the band width of the memory by using a sparse-matrix management library of software.
However, since these processes depend on the software, a large overhead is present upon access to the non-zero components. Moreover, upon access to the sparse matrix, massive time is taken if access according to data management methods of respective libraries is not used. Therefore, access cannot be made like that for a matrix formed by a normal two-dimensional layout, which is inconvenient. Conventionally, there has been hardware that carries out management so as to retain only non-zero components in a DRAM; however, there is a problem that processing upon rewrite is complex and has a large overhead.
On the other hand, generally, the processing speed of a processor or a hardware engine is higher than the data supply ability of a main memory such as a DRAM; therefore, a cache memory which compensates for the performance difference thereof is used in some cases. The cache memory is a memory such as a SRAM which exhibits a higher speed than the main memory, and the cache memory temporarily stores data in a data array. The processor can carry out high-speed processing by accessing the data in the cache memory.
If there are no data in the data array, the cache memory acquires data from the main memory in the unit of a cache line size (for example, 256 bytes) larger than an accessed data size. By accessing the main memory in the large unit, efficiency of the access to the main memory is improved. On the other hand, in a case in which data are in the data array, the cache memory can return data from the data array without acquisition of data from the main memory; therefore, the processor or the hardware engine can access the data at high speed.